1. Field of Invention
The present invention relates to a low voltage differential signal driver and a pre-emphasis circuit, and more particularly, to a low voltage differential signal driver with high switching speed and high resolution and a pre-emphasis circuit thereof.
2. Description of the Related Art
The low voltage differential signal (LVDS) technology is applied in data transmission systems. The LVDS generated by a line driver has a typical value of peak-to-peak voltage, ranging from 250 mV to 450 mV. In cases of high transmission rate, a low-voltage switch is helpful in reducing the power consumption. Therefore, LVDS technology is especially suitable for high-speed data transmission, such as video data processing. In fact, LVDS applications can be found, more or less, in professional video processing devices and electronic consumer products, such as flat panel display and notebook computers.
FIG. 1 is a schematic circuit drawing of a conventional low-voltage differential signal driver. Referring to FIG. 1, the conventional LVDS driver comprises the transistor M11, M12, M13 and M14. Wherein, the first source/drain end of the transistor M11 is connected to a voltage supply VDD via a driving current source I1 and the first source/drain end of the transistor M13. The gate end of the transistor M11 receives a driving signal VIN1. The second source/drain end of the transistor M11 is connected to the first source/drain end of the transistor M12 and one end of a load resistor Rt. Similarly, the gate end and the second source/drain end of the transistor M13 are connected to a driving signal VIN2 and the first source/drain end of the transistor M14, respectively, and the second source/drain end of the transistor M13 is also connected to another end of the load resistor Rt. In addition, the gate end and the second source/drain end of the transistor M12 are connected to the driving signal VIN2 and the ground via a resistor R1, respectively. The gate end and the second source/drain end of the transistor M14 are connected to the driving signal VIN1 and the second source/drain end of the transistor M12, respectively.
When the driving signal VIN1 is enabled, it would turn on the transistor M11 and M14. Meanwhile, the driving current generated by the driving current source I1 flows into the first source/drain end of the transistor M11, passes the node 103, and gets to the load resistor Rt in the direction indicated by arrow A. Then the driving current passes the node 105, then reaches the ground via the transistor M14 and the resistor R1. Whereas, when the driving signal VIN2 is enabled, the transistor M13 and M12 will be turned on. Meanwhile, the driving current flows into the first source/drain end of the transistor M13, passes the node 105, and gets to the load resistor Rt in the direction indicated by arrow B. Then, the driving current passes the node 103, and then reaches the ground via the first source/drain end of the transistor M12, the second source/drain end of the transistor M12 and the resistor R1.
The disadvantage of the LVDS driver shown in FIG. 1 is that the switching speed of the current passing through the load resistor Rt is limited by the size of the driving current source I1. That is, the switching speed between route A and B of the current passing through the load resistor Rt, is limited by the size of the driving current source I1, such that the switching speed of the LVDS driver becomes slower. The details can be referred to the U.S. Pat. No. 6,281,715.
To solve the above-described problem, the U.S. Pat. No. 6,281,715 also provides an LVDS driver. Referring to FIG. 2 in the U.S. Pat. No. 6,281,715, the disclosed LVDS driver generates an additional current ID2 to a current control circuit 201 by means of a current mirror circuit 207 at the instant of switching the current when flowing through the load resistor RL. Thus, the current control circuit 201 can utilize both the current ID1 and ID2 to increase the switching speed.
In the LVDS driver disclosed in the U.S. Pat. No. 6,281,715, five inverters ID1˜ID5 and an exclusive-NOR gate XNOR are used to receive an input signal IN and to control the turn-on sequence of the transistor M21, M22, M23 and M24. Therefore, these logic gates would take a lot of processing time. In particular, the delay when the signals travel through the exclusive-NOR gate consumes the most part of time.
In addition, due to the asynchrony between the control signal to turn on the transistor M25 and M27 and the control signal to turn on the transistor M26 and M28, the timing of turning on the transistor M25 and M26 is somewhat different from that of turning on the transistor M27 and M28. Consequently, the resolution performance of the LVDS driver disclosed in the U.S. Pat. No. 6,281,715 declines.